1. Field of the Invention
This invention relates to an integrated programmable logic arrangement (programmable logic array).
2. Description of the Prior Art
Logic arrangements of this type are generally known and are referred to in brief as PLA. For example, the publication of W. Carr & J. Mize: "MOS/LSI design and application", McGraw-Hill Book Co., New York, 1972, p. 229 to 258 describes such a logic arrangement, which basically comprises an AND-gate, an OR-gate, and of the associated drive- feedback- and output- circuits.
FIG. 1 is a block circuit diagram of a known arrangement of this type. Here, the AND-matrix is referenced 1 and the OR-matrix is referenced 2. The signals present at the inputs E.sub.1 to E.sub.n of the AND-matrix 1 are logic-linked in the matrices 1 and 2. The result of this logic-link is present at the outputs A.sub.1 to A.sub.n of the OR-matrix 2. Logic-linking signals are also present at the inputs E.sub.1 ' to E.sub.n ' of the feed-back loop 3. In the feedback loop 3, the information is delayed by a specific length of time, so that when the next item of information is present at the inputs E.sub.1 to E.sub.n of the AND-matrix 1, it can be logic-linked with the previous item of information present at the outputs A.sub.1 ' to A.sub.n ' of the feedback loop. It is thus possible to effect logic functions with a time delay (so-called sequential logic) with the aid of programmable logic arrangements.
The AND-matrix 1 may consist of individual gates, each gate consisting in turn of parallel-connected switching transistors. In each case, one gate terminal of each switching transistor is connected to a control line. For example, in the AND-matrix 1, the switching transistors 14 and 17 are transistors of the first gate. Here the switching transistor 14 is connected to the control line 141 which in turn is connected to the input E.sub.1. The switching transistor 17 is connected to the control line 171 which in turn is connected via the negator 19 to the input E.sub.2. On one side, the switching transistors 14 and 17 are connected to ground via the line 131, and on the other side they are connected to the gate line 111. The supply voltage U.sub.DD is connected to the gate line 111 via the load transistor 11 which is connected as a load transistor.
Individual gates, such as the gate composed of the transistors 24 and 26 in the OR-matrix 2, are arranged in corresponding manner.
Further details of known programmable logic arrangements of this type are given in earlier U.S. Ser. No. 633,959 and U.S. Pat. No. 3,974,366 issued on Aug. 10, 1976 of the same assignee.
Known programmable logic arrangements of this type are programmed with the aid of a mask during production. This creates the disadvantage that after production has been completed, it is no longer possible to change the logic pattern.